In SOI MOSFETs, electrical leakage between source and drain diffusions can occur in the SOI silicon layer at the interface with the back oxide layer. This leakage results from weak inversion at the back interface due to charge at the interface or in the back oxide. This charge may result from contamination introduced during processing, from trap generation at the interface or in the bulk of the back oxide during processing, from the operating environment (i.e. ionizing radiation), or due to the electrical operating conditions (giving rise to impact ionization).
In the past, with relatively thick SOI layers (&gt;200 nm) it was possible to tailor the vertical doping profile in the SOI MOSFET channels such that the doping concentration at the backside is greater than at the frontside of the SOI layer. An ion implantation having a peak near the back interface between the device layer and the insulating layer is used to achieve the desired doping profile (boron for the NFETs, phosphorus or arsenic for PFETs). This produced the effect of increasing the backside threshold voltage without increasing the frontside threshold voltage V.sub.t. Thus, it was possible to suppress backside leakage without seriously affecting the performance of the device.
With the thin SOI layers employed today (&lt;100 nm) attempts to increase the doping at the backside of the SOI significantly increase the doping at the frontside. This degrades the characteristics of the MOSFETs.
U.S. Pat. No. 5,231,045 illustrates a method of forming NMOS SOI integrated circuits, including the step of implanting aluminum ions into a substrate wafer prior to a bonding step in which two wafers are bonded together to form the SOI wafer. This method produces a uniform dopant concentration of Al across the entire wafer. If applied to CMOS processing, this method would leave implanted charge underneath both the NFETs and the PFETs. Although backside leakage in the NFETs is suppressed, this approach would have the unfortunate effect that the magnitude of the threshold for the PFETs will be lowered by the implanted ions and the PFET leakage current would be increased. This prior art work teaches away from implantation of Al through the device layer because of damage to the crystal structure of the device layer.